CiteWeb id: 19680000171

CiteWeb score: 998

DOI: 10.1109/JSSC.1968.1049925

This paper describes a technique for the design of two-signal four-quadrant multipliers, linear on both inputs and useful from dc to an upper frequency very close to the f/SUB t/ of the transistors comprising the circuit. The precision of the product is shown to be limited primarily by the matching of the transistors, particularly with reference to emitter-junction areas. Expressions are derived for the nonlinearities due to various causes.